The present invention disclosed herein relates to a method and device for repairing memory.
The development of a semiconductor process may increase the degree of integration in memory but also increase the probability of cell failure. Since the failure of a memory cell causes the reduction of a memory yield, a method for repairing the failure of a memory cell is suggested. Redundancy analysis (RA) means a method for preparing a spare memory for repairing the failure of a memory cell and replacing a failed memory cell. A good RA algorithm is required to derive a repair solution from a repairable circuit and have a short repair time. However, since finding a repair solution by disposing a two-dimensional spare memory in a failed memory cell is an NP-complete problem, as the size of a memory is greater, a repair time is increased rapidly. Therefore, a good RA algorithm is required to have a high repair efficiency and finish the repair with in a proper time.
Typically, a RA algorithm for repairing a line having a plurality of failures first in one line is mainly used for repair efficiency.